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Fundamentals of Small-Delay Defect Testing
Book chapter

Fundamentals of Small-Delay Defect Testing

M. Reddy Sudhakar and Maxwell Peter
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, pp.1-20
CRC Press, 1
2014
DOI: 10.1201/b15549-1

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Abstract

This chapter describes that the works to address tests of small-delay defects have focused on enhancing transition fault tests. Generation of such tests requires the automatic test pattern generation tool to be aware of the circuit delays. The application of a test pattern at a higher clock speed reduces the available system slack on all paths, thereby increasing the chances of detection of small-delay defects on all paths. Because traditional delay test methods target relatively large defects, including a more thorough coverage of small-delay defects can lead to significant improvements in quality levels. The test objective is to screen defective parts from manufactured devices. Defects could modify the functionality or performance of devices. Defects are physical and thus are not amenable to analysis by taking advantage of Boolean algebra used to design and analyze digital logic circuits. To facilitate analysis of defects and the derivation of tests, fault models are used to model defects.
 Pattern T1 Threshold Voltage Delay Fault Model Fault Coverage Fault Effect Faulty Line VLSI Device TDF Timing Aware ATPG Transition Fault Delay Fault Bridge Resistance Path Delay Fault Model ATPG Tool Modern CMOS Process Defect Size Fault Model Path Delay Fault Fault Site ATPG Signal Propagation Delays Decreasing Feature Sizes Bridging Fault Models Bridge Defect Stuck At-1 Fault

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