Book chapter
Optimizing SOC Test Resources Using Dual Sequences
VLSI-SOC: From Systems to Chips, pp.181-196
IFIP International Federation for Information Processing, Springer US
2006
DOI: 10.1007/0-387-33403-3_12
Abstract
In this paper, we propose a new data structure called dual sequences to represent SOC test schedules. Dual sequences are used together with a simulated annealing based procedure to optimize the SOC test application time and tester resources. The problems we consider are generation of optimal test schedules for SOCs and minimizing tester memory and test channels. Results of experiments conducted on ITC’02 benchmark SOCs show the effectiveness of the proposed method.
Details
- Title: Subtitle
- Optimizing SOC Test Resources Using Dual Sequences
- Creators
- Wei Zou - University of IowaChris C. N Chu - Iowa State UniversitySudhakar M Reddy - University of IowaIrith Pomeranz - Purdue University West Lafayette
- Resource Type
- Book chapter
- Publication Details
- VLSI-SOC: From Systems to Chips, pp.181-196
- Series
- IFIP International Federation for Information Processing
- DOI
- 10.1007/0-387-33403-3_12
- ISSN
- 1571-5736
- Publisher
- Springer US; Boston, MA
- Language
- English
- Date published
- 2006
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984196966502771
Metrics
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