Conference proceeding
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
2008 Design, Automation and Test in Europe, pp.1166-1171
03/2008
DOI: 10.1109/DATE.2008.4484836
Abstract
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthesis of the circuit. The stuck-at fault model is robust, but other fault models such as certain bridging fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. The ability to achieve 100% fault coverage, or understand why it is not achievable, is important since the requirement to achieve high test quality translates into a requirement to achieve complete fault coverage for target faults, regardless of the metrics used to measure test quality. We discuss a robust bridging fault model and its use as part of a test generation process for a non-robust bridging fault model (a non-robust bridging fault model may have to be used in order to capture the behavior of bridging defects). We also present experimental results related to the robust bridging fault model.
Details
- Title: Subtitle
- A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
- Creators
- I Pomeranz - Purdue University West LafayetteS.M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- 2008 Design, Automation and Test in Europe, pp.1166-1171
- Publisher
- IEEE
- DOI
- 10.1109/DATE.2008.4484836
- ISSN
- 1530-1591
- eISSN
- 1558-1101
- Language
- English
- Date published
- 03/2008
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197337502771
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