Conference proceeding
A Cube-Aware Compaction Method for Scan ATPG
2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, pp.98-103
01/2014
DOI: 10.1109/VLSID.2014.24
Abstract
We propose a test-cube aware dynamic compaction method for reducing the test set size generated by scan ATPG. In the initial phase of ATPG, when the generated test cubes are significantly compatible, we start with a local cube merging approach. Then, we switch to a compacted cube-generation approach, when the compatibility of test cubes decrease. We propose efficient heuristics for merging test cubes and writing them out during the cube-merging phase. We introduce a novel reasoning analysis technique to learn cube-independent untestable faults and, avoid targeting them repeatedly during the compacted-cube generation phase. On latest Intel microprocessor designs, we are able to achieve up to 2.3X compaction with 20% run-time over-head, on top of on-chip hardware compression.
Details
- Title: Subtitle
- A Cube-Aware Compaction Method for Scan ATPG
- Creators
- Sharada Jha - IntelKameshwar Chandrasekar - IntelWeixin Wu - IntelRamesh Sharma - IntelSanjay Sengupta - IntelSudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, pp.98-103
- Publisher
- IEEE
- DOI
- 10.1109/VLSID.2014.24
- ISSN
- 1063-9667
- eISSN
- 2380-6923
- Language
- English
- Date published
- 01/2014
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197309102771
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