A DFT approach for path delay faults in interconnected circuits

Irith Pomeranz; Sudhakar M Reddy

doi:10.1109/ATS.2003.1250786

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Conference proceeding

A DFT approach for path delay faults in interconnected circuits

Irith Pomeranz and Sudhakar M Reddy

2003 Test Symposium, Vol.2003-, pp.72-75

2003

DOI: 10.1109/ATS.2003.1250786

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Abstract

We propose a new DFT approach for path delay faults in interconnected circuits. The proposed approach places multiplexers on the interface between two circuits in order to create new testable paths through the interconnection. The new testable paths allow us to increase the number of paths tested in each circuit. This approach does not require interconnected circuits to be isolated by test wrappers.

Combinational logic circuits

Design for testability

Fault diagnosis

Logic circuit testing

Details

Title: Subtitle: A DFT approach for path delay faults in interconnected circuits
Creators: Irith Pomeranz - Purdue University West Lafayette
Sudhakar M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 2003 Test Symposium, Vol.2003-, pp.72-75
Publisher: IEEE
DOI: 10.1109/ATS.2003.1250786
ISSN: 1081-7735
eISSN: 2377-5386
Language: English
Date published: 2003
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197525102771

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