Conference proceeding
A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops
2006 15th Asian Test Symposium, Vol.2006, pp.287-292
11/2006
DOI: 10.1109/ATS.2006.261033
Abstract
Field programmable memory BIST controllers are becoming a necessity to target manufacturing defects in embedded memories. For 65nm and below, random defects are not the only ones affecting the yield of a process. Systematic as well as parametric defects are now the predominant causes of memory failures and have to be addressed. Conventional memory BIST algorithms are usually targeted to catch random defects. In order to catch such systematic and parametric defects, it is necessary to have the flexibility to apply new algorithms to embedded memories after manufacturing. In this paper, a field programmable memory BIST architecture is proposed to support multiple loops within a test step of an algorithm, including nested loops. These controllers, therefore, guarantee supporting complex algorithm necessary to target defects during failure analysis that could help yield ramp up or reduce test escapes. In addition, the proposed architecture is modular in nature and allows optimizing the complexity of the controller along with area and performance
Details
- Title: Subtitle
- A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops
- Creators
- Xiaogang Du - Mentor GraphicsNilanjan Mukherjee - Mentor GraphicsChris Hill - Mentor GraphicsWu-Tung Cheng - Mentor GraphicsSudhakar Reddy
- Resource Type
- Conference proceeding
- Publication Details
- 2006 15th Asian Test Symposium, Vol.2006, pp.287-292
- DOI
- 10.1109/ATS.2006.261033
- ISSN
- 1081-7735
- eISSN
- 2377-5386
- Publisher
- IEEE
- Language
- English
- Date published
- 11/2006
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197320202771
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