Conference proceeding
A New Approach to Test Generation and Test Compaction for Scan Circuits
Proceedings of the conference on design, automation and test in europe, Vol.1, pp.11000-1005
DATE '03
03/03/2003
DOI: 10.1109/DATE.2003.1253735
Abstract
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors. Under this approach, the scan-in, scan-select and scan-out lines are treated as conventional primary inputs or primary outputs of the circuit. As a result, limited scan operations, where scan chains are shifted a number of times smaller than their lengths, are incorporated naturally into the test sequences generated by this approach. This leads to very aggressive compaction, resulting in test sequences with the lowest known test application times for benchmark circuits.
Details
- Title: Subtitle
- A New Approach to Test Generation and Test Compaction for Scan Circuits
- Creators
- Irith PomeranzSudhakar Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the conference on design, automation and test in europe, Vol.1, pp.11000-1005
- Publisher
- IEEE Computer Society
- Series
- DATE '03
- DOI
- 10.1109/DATE.2003.1253735
- ISSN
- 1530-1591
- eISSN
- 1558-1101
- Language
- English
- Date published
- 03/03/2003
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197351502771
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