A Parallel PLA Minimization Program

R Galivanche; S.M Reddy

doi:10.1145/37888.37983

Back

Conference proceeding

A Parallel PLA Minimization Program

R Galivanche and S.M Reddy

24th ACM/IEEE Design Automation Conference, pp.600-607

ACM/IEEE Conference on Design Automation, 24 (Miami Beach, Florida, USA, 06/28/1987–07/01/1987)

1987

DOI: 10.1145/37888.37983

View Online

Abstract

In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The parallel algorithm was implemented on a shared memory multicomputer system. In the course of development of the parallel algorithm, some changes were made to ESPRESSO-MV which resulted in lower computing time. Experimental results using 105 PLAs are included.

Microprocessors

Parallel Algorithms

Automatic control

Concurrent computing

Logic functions

Minimization methods

Permission

Programmable logic arrays

Time sharing computer systems

Very large scale integration

Details

Title: Subtitle: A Parallel PLA Minimization Program
Creators: R Galivanche - Motorola
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 24th ACM/IEEE Design Automation Conference, pp.600-607
Conference: ACM/IEEE Conference on Design Automation, 24 (Miami Beach, Florida, USA, 06/28/1987–07/01/1987)
DOI: 10.1145/37888.37983
ISSN: 0738-100X
eISSN: 2374-8818
Publisher: ACM
Language: English
Date published: 1987
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984198013402771

Metrics

17 Record Views