Conference proceeding
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
Proceedings of the 2002 Asia and South Pacific Design Automation Conference, pp.677-682
ASP-DAC '02
01/07/2002
DOI: 10.1109/ASPDAC.2002.995013
Abstract
We describe a built-in test pattern generation method for scan circuits.The method is based on partitioning and storage of test sets.Under this method,a precomputed test set is partitioned into several sets containing values of different primary inputs or state variables.The on-chip test set is obtained by implementing the Cartesian product of the various sets.The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time.
Details
- Title: Subtitle
- A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
- Creators
- Irith PomeranzSudhakar Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the 2002 Asia and South Pacific Design Automation Conference, pp.677-682
- Series
- ASP-DAC '02
- DOI
- 10.1109/ASPDAC.2002.995013
- Publisher
- IEEE Computer Society
- Language
- English
- Date published
- 01/07/2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197269302771
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