A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults

N Devtaprasanna; A Gunda; P Krishnamurthy; S.M Reddy; I Pomeranz

doi:10.1109/ETS.2006.8

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Conference proceeding

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults

N Devtaprasanna, A Gunda, P Krishnamurthy, S.M Reddy and I Pomeranz

Eleventh IEEE European Test Symposium (ETS'06), Vol.2006, pp.185-192

2006

DOI: 10.1109/ETS.2006.8

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Abstract

Detection of transistor stuck-open faults in CMOS circuits requires two-pattern tests. Transition delay fault model is commonly used to model delay causing defects and it also requires two-pattern tests. In this paper we examine the relationship between the two fault models and propose a method for generating test patterns that achieve maximum coverage of both faults. In the proposed method we use an ATPG program for transition delay faults to generate test patterns for both faults. Experimental results are presented to evaluate the effectiveness of our approach

Automatic test pattern generation

Circuit faults

Circuit testing

Delay

Electrical fault detection

Fault detection

Logic testing

Power supplies

System testing

Test pattern generators

Details

Title: Subtitle: A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults
Creators: N Devtaprasanna - University of Iowa
A Gunda - LSI Corporation
P Krishnamurthy - LSI Corporation
S.M Reddy - University of Iowa
I Pomeranz - Purdue University West Lafayette
Resource Type: Conference proceeding
Publication Details: Eleventh IEEE European Test Symposium (ETS'06), Vol.2006, pp.185-192
DOI: 10.1109/ETS.2006.8
ISSN: 1530-1877
eISSN: 1558-1780
Publisher: IEEE
Language: English
Date published: 2006
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197331702771

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