A divide-and-conquer approach to test generation for large synchronous sequential circuits

I Pomeranz; S.M Reddy

doi:10.1109/FTCS.1992.243579

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Conference proceeding

A divide-and-conquer approach to test generation for large synchronous sequential circuits

I Pomeranz and S.M Reddy

[1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing, pp.230-237

1992

DOI: 10.1109/FTCS.1992.243579

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Abstract

A method for generating tests for synchronous sequential circuits that does not use the complete circuit description is proposed, to allow true divide-and-conquer to be applied to test generation. The method is based on the generation of primary input sequences such that for as many sequences generated by the adjacent subcircuits as possible, a test sequence for the subcircuit under consideration would result. Repeated application of test sequences is proposed as a means of increasing the probability of fault detection. Experimental results are presented to show that the method is applicable to subcircuits of large sequential circuits.< >

Circuit faults

Circuit testing

Cities and towns

Contracts

Fault detection

Hardware

Performance evaluation

Sequential analysis

Sequential circuits

Synchronous generators

Details

Title: Subtitle: A divide-and-conquer approach to test generation for large synchronous sequential circuits
Creators: I Pomeranz - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing, pp.230-237
DOI: 10.1109/FTCS.1992.243579
Publisher: IEEE
Language: English
Date published: 1992
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197555902771

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