A fault simulation based test pattern generator for synchronous sequential circuits

Ruifeng Guo; I Pomeranz; S.M Reddy

doi:10.1109/VTEST.1999.766674

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Conference proceeding

A fault simulation based test pattern generator for synchronous sequential circuits

Ruifeng Guo, I Pomeranz and S.M Reddy

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), pp.260-267

IEEE VLSI Test Symposium, 17 (Dana Point, California, USA, 04/25/1999 - 04/29/1999)

1999

DOI: 10.1109/VTEST.1999.766674

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Abstract

We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at low computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures.

Genetics

Circuit faults

Circuit simulation

Circuit testing

Computational modeling

Logic testing

Sequential analysis

Sequential circuits

Synchronous generators

Test pattern generators

Details

Title: Subtitle: A fault simulation based test pattern generator for synchronous sequential circuits
Creators: Ruifeng Guo - University of Iowa
I Pomeranz - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), pp.260-267
Conference: IEEE VLSI Test Symposium, 17 (Dana Point, California, USA, 04/25/1999 - 04/29/1999)
Publisher: IEEE
DOI: 10.1109/VTEST.1999.766674
ISSN: 1093-0167
eISSN: 2375-1053
Language: English
Date published: 1999
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984198004202771

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