Conference proceeding
A flexible path selection procedure for path delay fault testing
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), pp.152-159
IEEE VLSI Test Symposium, 17 (Dana Point, California, USA, 04/25/1999 - 04/29/1999)
1999
DOI: 10.1109/VTEST.1999.766659
Abstract
We describe a path selection procedure that selects target faults for path delay fault test generation. Since large numbers of path delay faults may be untestable, the proposed procedure does not select a fixed set of paths. Instead, it provides compactly represented subsets of paths, referred to as super-paths, and allows the test generation procedure to select one path out of each subset based on testability considerations.
Details
- Title: Subtitle
- A flexible path selection procedure for path delay fault testing
- Creators
- I Pomeranz - University of IowaS.M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), pp.152-159
- Conference
- IEEE VLSI Test Symposium, 17 (Dana Point, California, USA, 04/25/1999 - 04/29/1999)
- Publisher
- IEEE
- DOI
- 10.1109/VTEST.1999.766659
- ISSN
- 1093-0167
- eISSN
- 2375-1053
- Language
- English
- Date published
- 1999
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197920402771
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