Conference proceeding
A generalized test generation procedure for path delay faults
Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224), Vol.1998-, pp.274-283
1998
DOI: 10.1109/FTCS.1998.689478
Abstract
Recent studies suggest that it is necessary to generalize the test generation process for path delay faults in order to accommodate various effects that determine the worst-case delay of a path. However, these effects may be too complex to be captured accurately or considered explicitly, especially for large circuits. To alleviate this problem, we propose a test generation approach that generates multiple tests for each path delay fault based on a comprehensive set of conditions under which the worst-case delays are likely to occur. In this way, accurate modeling of delays is not necessary. We describe a specific test generation procedure to demonstrate this approach. The test generation procedure produces, for every target path, two-pattern tests where the first patterns bring every possible combination of values to the off-path inputs. We present experimental results to show the feasibility of a test generation procedure based on this approach.
Details
- Title: Subtitle
- A generalized test generation procedure for path delay faults
- Creators
- I Pomeranz - University of IowaS.M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224), Vol.1998-, pp.274-283
- Publisher
- IEEE
- DOI
- 10.1109/FTCS.1998.689478
- ISSN
- 0731-3071
- eISSN
- 2375-124X
- Language
- English
- Date published
- 1998
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197417702771
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