Conference proceeding
A low power pseudo-random BIST technique
ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, pp.468-473
2002
DOI: 10.1109/ICCD.2002.1106815
Abstract
Peak power consumption during testing is an important concern. For scan designs, a high level of switching activity is created in the circuit during scan shifts, which increases power consumption considerably. In this paper we propose a pseudo-random BIST scheme for scan designs, which reduces the peak power consumption as well as the average power consumption as measured by the switching activity in the circuit. The method reduces the switching activity in the scan chains and the activity in the circuit under test by limiting the scan shifts to a portion of the scan chain structure using scan chain disable. Experimental results on various benchmark circuits demonstrate that the technique reduces the switching activity caused by scan shifts.
Details
- Title: Subtitle
- A low power pseudo-random BIST technique
- Creators
- N Z Basturkmen - University of IowaS M Reddy - University of IowaI Pomeranz - Purdue University West Lafayette
- Resource Type
- Conference proceeding
- Publication Details
- ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, pp.468-473
- DOI
- 10.1109/ICCD.2002.1106815
- Language
- English
- Date published
- 2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984232099302771
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