Sign in
A new test generation method for sequential circuits
Conference proceeding

A new test generation method for sequential circuits

Dong Ho Lee and Sudhakar M Reddy
Computer-Aided Design: International Conference on (ICCAD '91), pp.446-449
01/01/1992
DOI: 10.1109/ICCAD.1991.185300

View Online

Abstract

A novel test generation method for synchronous sequential circuits is proposed. Among the new ideas employed are: 1) efficiently maintaining path information using an extended value system in forward time processing, and 2) efficiently enumerating cubes for state justification in backward time processing. Experimental results show that the proposed method is effective in generating high coverage tests for sequential circuits.

Details

Metrics

2 Record Views