Conference proceeding
A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits
Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02), Vol.2002-, pp.110-115
2002
DOI: 10.1109/ATS.2002.1181696
Abstract
We describe a built-in test pattern generation method for delay faults in scan circuits based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the stored sets. The sizes of the sets are minimized before they are stored on-chip in order to reduce the storage requirements and the test application time. The delay fault model we consider is the transition fault model.
Details
- Title: Subtitle
- A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02), Vol.2002-, pp.110-115
- DOI
- 10.1109/ATS.2002.1181696
- ISSN
- 1081-7735
- eISSN
- 2377-5386
- Publisher
- IEEE
- Language
- English
- Date published
- 2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197213902771
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