Conference proceeding
A partitioning and storage based built-in test pattern generation method for synchronous sequential circuits
Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001, pp.148-153
2001
DOI: 10.1109/ICCD.2001.955017
Abstract
We describe a built-in test pattern generation method for synchronous sequential circuits based on partitioning and storage of test subsequences. Under this method, a set of subsequences /spl Psi/ is stored on-chip. On-chip test sequences are obtained by implementing a subset of the Cartesian product /spl Psi/x/spl Psi/x/spl middot//spl middot//spl middot/x/spl Psi/. The set /spl Psi/ is obtained by iterative partitioning of a precomputed test sequence T. The number of subsequences in /spl Psi/ is minimized at every iteration in order to reduce the final storage requirements, the test application time, and the computational effort required to produce the final set /spl Psi/.
Details
- Title: Subtitle
- A partitioning and storage based built-in test pattern generation method for synchronous sequential circuits
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001, pp.148-153
- DOI
- 10.1109/ICCD.2001.955017
- ISSN
- 1063-6404
- eISSN
- 2576-6996
- Publisher
- IEEE
- Language
- English
- Date published
- 2001
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197304202771
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