A partitioning technique for identification of error-capturing scan cells in scan-BIST

Chaowen Yu; S.M Reddy; I Pomeranz

doi:10.1109/IOLTS.2006.9

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Conference proceeding

A partitioning technique for identification of error-capturing scan cells in scan-BIST

Chaowen Yu, S.M Reddy and I Pomeranz

12th IEEE International On-Line Testing Symposium (IOLTS'06), Vol.2006, pp.6 pp-42

2006

DOI: 10.1109/IOLTS.2006.9

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Abstract

The paper proposes a two-step scan cell partitioning scheme to identify the error-capturing scan cells in a scan-BIST environment. In the first step, a deterministic partitioning scheme is used, whose target is to maximize the correlations between different scan cells in fault diagnosis since different scan cells have very different probabilities of capturing fault effects. In the second step, a previously proposed random partitioning scheme is used to generate additional partitions. Experimental results are reported on the five largest ISCAS'89 benchmark circuits and compared with that for the random partitioning scheme and another earlier work using interval-based partitioning scheme

Chaos

Automatic testing

Built-in self-test

Circuit faults

Circuit testing

Cities and towns

Design for testability

Fault diagnosis

Integrated circuit testing

Very large scale integration

Details

Title: Subtitle: A partitioning technique for identification of error-capturing scan cells in scan-BIST
Creators: Chaowen Yu - University of Iowa
S.M Reddy - University of Iowa
I Pomeranz - Purdue University West Lafayette
Resource Type: Conference proceeding
Publication Details: 12th IEEE International On-Line Testing Symposium (IOLTS'06), Vol.2006, pp.6 pp-42
DOI: 10.1109/IOLTS.2006.9
ISSN: 1942-9398
eISSN: 1942-9401
Publisher: IEEE
Language: English
Date published: 2006
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197298902771

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