A test interface for built-in test of non-isolated scanned cores

Irith Pomeranz; Sudhakar M Reddy; Yervant Zorian

doi:10.1109/VTEST.2003.1197677

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Conference proceeding

A test interface for built-in test of non-isolated scanned cores

Irith Pomeranz, Sudhakar M Reddy and Yervant Zorian

Proceedings. 21st VLSI Test Symposium, 2003, Vol.2003-, pp.371-376

2003

DOI: 10.1109/VTEST.2003.1197677

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Abstract

We consider the problem of built-in test pattern generation for non-isolated scanned cores. When two such cores are interconnected, a block of combinational logic that spans both cores may be created. Our goal is to provide a solution for built-in testing of logic that spans multiple cores. Starting from a given test-pattern generator (TPG), we propose a design-for-testability approach to improve the fault coverage achieved by the TPG. This approach is based on designing the interfaces between pairs of cores such that they support the testing of both cores. The proposed approach does not require any modifications to the cores themselves. In a vast majority of the benchmark circuits considered, the proposed approach results in 100% fault coverage.

Benchmark testing

Built-in self-test

Circuit faults

Circuit testing

Cities and towns

Controllability

Integrated circuit interconnections

Logic testing

Observability

Test pattern generators

Details

Title: Subtitle: A test interface for built-in test of non-isolated scanned cores
Creators: Irith Pomeranz - Purdue University West Lafayette
Sudhakar M Reddy
Yervant Zorian
Resource Type: Conference proceeding
Publication Details: Proceedings. 21st VLSI Test Symposium, 2003, Vol.2003-, pp.371-376
DOI: 10.1109/VTEST.2003.1197677
ISSN: 1093-0167
eISSN: 2375-1053
Publisher: IEEE
Language: English
Date published: 2003
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197354502771

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