Conference proceeding
A unified fault model and test generation procedure for interconnect opens and bridges
European Test Symposium (ETS'05), Vol.2005, pp.22-27
2005
DOI: 10.1109/ETS.2005.6
Abstract
A unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. Additionally the model does not require accurate device level circuit models to achieve desired accuracy. Efficient methods for fault simulation and test generation are discussed and experimental results on benchmark circuits and industrial designs are presented. The experimental results presented show that the tests generated using simpler versions of the proposed fault model achieve higher defect coverage than the tests using two currently popular methods to derive high defect coverage tests.
Details
- Title: Subtitle
- A unified fault model and test generation procedure for interconnect opens and bridges
- Creators
- Gang Chen - University of IowaSudhakar Reddy - University of IowaIrith Pomeranz - Purdue University West LafayetteJanusz Rajski - Mentor Graphics (United States)Piet Engelke - Albert-Ludwigs-University#TAB#Bernd Becker - Albert-Ludwigs-University#TAB#
- Resource Type
- Conference proceeding
- Publication Details
- European Test Symposium (ETS'05), Vol.2005, pp.22-27
- DOI
- 10.1109/ETS.2005.6
- ISSN
- 1530-1877
- eISSN
- 1558-1780
- Publisher
- IEEE
- Language
- English
- Date published
- 2005
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984196968702771
Metrics
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