ATE assisted test response compaction

J M Howard; S M Reddy; I Pomeranz

doi:10.1109/VDAT.2010.5496704

Back

Conference proceeding

ATE assisted test response compaction

J M Howard, S M Reddy and I Pomeranz

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, pp.112-115

04/2010

DOI: 10.1109/VDAT.2010.5496704

View Online

Abstract

A new method for achieving test response compaction is proposed. The method involves testers to achieve additional compaction, without compromising fault coverage, beyond what may be already achieved using on-chip response compactors. The method does not add additional logic or modify the circuit under test or require additional tests and thus can be used with any design including legacy designs. Simple heuristic procedures are used to achieve additional compaction. Experimental results on larger ISCAS-89 circuits show the effectiveness of the method.

Automatic testing

Chromium

Circuit faults

Circuit testing

Compaction

Integrated circuit testing

Logic design

Logic testing

Sequential analysis

Sequential circuits

Details

Title: Subtitle: ATE assisted test response compaction
Creators: J M Howard - University of Iowa
S M Reddy - University of Iowa
I Pomeranz - Purdue University West Lafayette
Resource Type: Conference proceeding
Publication Details: Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, pp.112-115
DOI: 10.1109/VDAT.2010.5496704
Publisher: IEEE
Language: English
Date published: 04/2010
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197170302771

Metrics

23 Record Views