ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction

Santiago Remersaro; Janusz Rajski; Thomas Rinderknecht; Sudhakar M Reddy; Irith Pomeranz

doi:10.1109/DFT.2008.39

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Conference proceeding

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction

Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M Reddy and Irith Pomeranz

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, pp.385-393

10/2008

DOI: 10.1109/DFT.2008.39

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Abstract

As digital circuits grow in gate count so does the data volume required for manufacturing test. To address this problem several test compression techniques have been developed. This paper presents a novel and scalable technique for inserting observation points to aid compression by reducing pattern count and data volume. Experimental results presented for industrial circuits demonstrate the effectiveness of the method.

Iron

ATPG

Automatic test pattern generation

Circuit faults

compact test sets

Compaction

Databases

Integrated circuit modeling

Logic gates

test compression

test point insertion

Details

Title: Subtitle: ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction
Creators: Santiago Remersaro - University of Iowa
Janusz Rajski - Mentor Graphics (United States)
Thomas Rinderknecht - Mentor Graphics (United States)
Sudhakar M Reddy - University of Iowa
Irith Pomeranz - Purdue University West Lafayette
Resource Type: Conference proceeding
Publication Details: 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, pp.385-393
DOI: 10.1109/DFT.2008.39
ISSN: 1550-5774
eISSN: 2377-7966
Publisher: IEEE
Language: English
Date published: 10/2008
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197451102771

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