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Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations
Conference proceeding

Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations

Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski and Sudhakar M. Reddy
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings
01/01/2021
DOI: 10.1109/VTS52500.2021.9794207

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Abstract

Conference Title: 2022 IEEE 40th VLSI Test Symposium (VTS) Conference Start Date: 2022, April 25 Conference End Date: 2022, April 27 Conference Location: San Diego, CA, USATest cost has become a critical issue for large industrial integrated circuits. Various test compression techniques have been adopted in the industry to reduce test cost. However, appropriate input and output channel counts must be selected to utilize the test compression technology best. This paper presents an efficient and effective method to estimate the test pattern counts under different compression configurations for the Embedded Deterministic Test (EDT) compression technique. In searching for the accurate estimation method, we build mathematical models that reveal the internal relationship among different compression configurations. The models are established based on novel theoretical analysis as well as actual experimental data. Accurate estimation of test pattern counts for a wide range of compression configurations can be obtained based on the results of only two ATPG runs. Experimental results on nine industrial circuits show that the average error rate of pattern count estimation is about 5%, with very few outliers. With the proposed method, a test compression designer can easily pick the best input and output channel configuration to fit the design needs.
Configuration management Integrated circuits Outliers (statistics) Very large scale integration

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