Sign in
An Enhanced Logic BIST Architecture for Online Testing
Conference proceeding

An Enhanced Logic BIST Architecture for Online Testing

F Yang, S Chakravarty, N Devta-Prasanna, S.M Reddy and I Pomeranz
2008 14th IEEE International On-Line Testing Symposium, pp.10-15
07/2008
DOI: 10.1109/IOLTS.2008.48

View Online

Abstract

Built-in self-test Circuit faults Circuit testing Cities and towns Clocks Electrical fault detection Fault detection Flip-flops Flush Test Logic BIST Logic circuits Logic testing Online Testing Stuck-open Faults

Details

Metrics

Logo image