Conference proceeding
An approach to test compaction for scan circuits that enhances at-speed testing
38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, pp.156-161
2001
DOI: 10.1145/378239.378390
Abstract
We propose a new approach to the generation of compact test sets for scan circuits. Compaction refers here to a reduction in the test application time. The proposed procedure generates an initial test set that is likely to have a low test application time. It then applies an existing static compaction procedure to this initial test set to further compact it. As a by-product, the proposed procedure also results in long primary input sequences, which are applied at-speed. This contributes to the detection of delay defects. We demonstrate through experimental results the advantages of this approach over earlier ones as a method for generating test sets with minimal test application time and long primary input sequences.
Details
- Title: Subtitle
- An approach to test compaction for scan circuits that enhances at-speed testing
- Creators
- Irith PomeranzSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- 38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, pp.156-161
- DOI
- 10.1145/378239.378390
- Language
- English
- Date published
- 2001
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984232098802771
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