An improved source design for scan BIST

Chaowen Yu; Wei LI; Sudhakar M Reddy; Irith Pomeranz

doi:10.1109/OLT.2003.1214375

Back

Conference proceeding

An improved source design for scan BIST

Chaowen Yu, Wei LI, Sudhakar M Reddy and Irith Pomeranz

9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003, pp.106-110

2003

DOI: 10.1109/OLT.2003.1214375

View Online

Abstract

Recently, Markov sources were shown to achieve 100% fault efficiency at low area overhead when used as pseudo-random pattern generators in scan BIST. In this paper we give a new method of designing Markov sources. The new design attempts to match probabilities of 1 to 0 and 0 to 1 transitions in consecutive bits of a set of test vectors, taking into account that the transition probabilities may be different for different bit positions. Experimental results show that the proposed method considerably reduces the hardware overhead and test lengths required to achieve 100% fault coverage.

Chaos

Built-in self-test

Circuit faults

Circuit testing

Cities and towns

Design methodology

Electrical fault detection

Fault detection

Hardware

Logic testing

Details

Title: Subtitle: An improved source design for scan BIST
Creators: Chaowen Yu - University of Iowa
Wei LI - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Sudhakar M Reddy - University of Iowa
Irith Pomeranz - Purdue University West Lafayette
Resource Type: Conference proceeding
Publication Details: 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003, pp.106-110
DOI: 10.1109/OLT.2003.1214375
Publisher: IEEE
Language: English
Date published: 2003
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197556802771

Metrics

23 Record Views