Conference proceeding
Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation
2012 25th International Conference on VLSI Design, pp.382-387
01/2012
DOI: 10.1109/VLSID.2012.101
Abstract
Test pattern generation for sequential circuits benefits from scanning strategies as these allow the justification of arbitrary circuit states. However, some of these states may be unreachable during normal operation. This results in non-functional operation which may lead to abnormal circuit behaviour and result in over-testing. In this work, we present a versatile approach that combines a highly adaptable SAT-based path-enumeration algorithm with a model-checking solver for invariant properties that relies on the theory of Craig interpolants to prove the unreachability of circuit states. The method enumerates a set of longest sensitisable paths and yields test sequences of minimal length able to sensitise the found paths starting from a given circuit state. We present detailed experimental results on the reach ability of sensitisable paths in ITC 99 circuits.
Details
- Title: Subtitle
- Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation
- Creators
- Matthias Sauer - University of FreiburgStefan Kupferschmid - University of FreiburgAlexander Czutro - University of FreiburgSudhakar Reddy - University of IowaBernd Becker - University of Freiburg
- Resource Type
- Conference proceeding
- Publication Details
- 2012 25th International Conference on VLSI Design, pp.382-387
- Publisher
- IEEE
- DOI
- 10.1109/VLSID.2012.101
- ISSN
- 1063-9667
- eISSN
- 2380-6923
- Language
- English
- Date published
- 01/2012
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197555002771
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