At-speed delay testing of synchronous sequential circuits

I Pomeranz; S.M Reddy

doi:10.1109/DAC.1992.227840

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Conference proceeding

At-speed delay testing of synchronous sequential circuits

I Pomeranz and S.M Reddy

[1992] Proceedings 29th ACM/IEEE Design Automation Conference, pp.177-181

ACM/IEEE Design Automation Conference, 29 (Anaheim, California, 06/08/1992 - 06/12/1992)

1992

DOI: 10.1109/DAC.1992.227840

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Abstract

Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length.< >

Circuit faults

Circuit testing

Clocks

Combinational circuits

Delay effects

Flip-flops

Robustness

Sequential analysis

Sequential circuits

System testing

Details

Title: Subtitle: At-speed delay testing of synchronous sequential circuits
Creators: I Pomeranz - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M Reddy - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Resource Type: Conference proceeding
Publication Details: [1992] Proceedings 29th ACM/IEEE Design Automation Conference, pp.177-181
Conference: ACM/IEEE Design Automation Conference, 29 (Anaheim, California, 06/08/1992 - 06/12/1992)
Publisher: IEEE Comput. Soc. Press
DOI: 10.1109/DAC.1992.227840
ISSN: 0738-100X
eISSN: 2374-8818
Language: English
Date published: 1992
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197911002771

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