At-speed scan test with low switching activity

Elham K Moghaddam; Janusz Rajski; Sudhakar M Reddy; Mark Kassab

doi:10.1109/VTS.2010.5469580

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Conference proceeding

At-speed scan test with low switching activity

Elham K Moghaddam, Janusz Rajski, Sudhakar M Reddy and Mark Kassab

2010 28th VLSI Test Symposium (VTS), pp.177-182

04/2010

DOI: 10.1109/VTS.2010.5469580

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Abstract

This paper presents a novel method to generate test vectors that mimic functional operation from switching activity point of view. The method uses states obtained by applying a number of functional clock cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

Law

At-speed test

Circuit testing

Cities and towns

Clocks

Fault detection

Graphics

Hamming distance

IR-drop

Legal factors

Low power tests

scan design

Sequential analysis

Switching activity

Very large scale integration

Details

Title: Subtitle: At-speed scan test with low switching activity
Creators: Elham K Moghaddam - University of Iowa
Janusz Rajski - Mentor Graphics
Sudhakar M Reddy - University of Iowa
Mark Kassab - Mentor Graphics
Resource Type: Conference proceeding
Publication Details: 2010 28th VLSI Test Symposium (VTS), pp.177-182
DOI: 10.1109/VTS.2010.5469580
ISSN: 1093-0167
eISSN: 2375-1053
Publisher: IEEE
Language: English
Date published: 04/2010
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197360202771

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