Built-in generation of weighted test sequences for synchronous sequential circuits

Irith Pomeranz; Sudhakar M Reddy

doi:10.1109/DATE.2000.840287

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Conference proceeding

Built-in generation of weighted test sequences for synchronous sequential circuits

Irith Pomeranz and Sudhakar M Reddy

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), pp.298-304

2000

DOI: 10.1109/DATE.2000.840287

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Abstract

We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficient to achieve complete coverage of stuck-at faults, since these weights are sufficient to reproduce any specific test pattern. For sequential circuits, the weights we use are defined based on subsequences of a deterministic test sequence. Such weights allow us to reproduce parts of the test sequence, and help ensure that complete fault coverage would be obtained by the weighted test sequences generated.

Circuit faults

Circuit testing

Cities and towns

Combinational circuits

Delay

Electrical fault detection

Fault detection

Sequential analysis

Sequential circuits

Synchronous generators

Details

Title: Subtitle: Built-in generation of weighted test sequences for synchronous sequential circuits
Creators: Irith Pomeranz - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Sudhakar M Reddy
Resource Type: Conference proceeding
Publication Details: Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), pp.298-304
Publisher: IEEE
DOI: 10.1109/DATE.2000.840287
ISSN: 1530-1591
eISSN: 1558-1101
Language: English
Date published: 2000
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197420402771

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