Conference proceeding
Built-in test generation for synchronous sequential circuits
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), pp.421-426
1997
DOI: 10.1109/ICCAD.1997.643570
Abstract
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed test application. We introduce a uniform, parametrized structure for test pattern generation. By matching the parameters of the test pattern generator to the circuit-under-test, high fault coverage is achieved. In many cases, the fault coverage is equal to the fault coverage that can be achieved by deterministic test sequences. We also investigate a method to minimize the size of the test pattern generator, and study its effectiveness alone and in conjunction with the insertion of test-points.
Details
- Title: Subtitle
- Built-in test generation for synchronous sequential circuits
- Creators
- Irith Pomeranz - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USASudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), pp.421-426
- Publisher
- IEEE
- DOI
- 10.1109/ICCAD.1997.643570
- ISSN
- 1092-3152
- Language
- English
- Date published
- 1997
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197197202771
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