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Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences
Conference proceeding

Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences

Irith Pomeranz and Sudhakar Reddy
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, pp.754-759
DAC '99
06/01/1999
DOI: 10.1145/309847.310052

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