Circuit Independent Weighted Pseudo-Random BIST Pattern Generator

Chaowen Yu; Sudhakar M Reddy; Irith Pomeranz

doi:10.1109/ATS.2005.37

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Conference proceeding

Circuit Independent Weighted Pseudo-Random BIST Pattern Generator

Chaowen Yu, Sudhakar M Reddy and Irith Pomeranz

14th Asian Test Symposium (ATS'05), Vol.2005, pp.132-137

2005

DOI: 10.1109/ATS.2005.37

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Abstract

This paper describes a circuit independent weighted pseudo random BIST pattern generator based on bit-flipping. The circuit dependent data is stored in memories so that different circuits can use the same BIST structure by only changing the data in the memories. New approaches are proposed for compressing and storing the bit-flipping data. Experimental results show that the proposed method reduces the size of the memory considerably while using similar test lengths as a recent method based on bit-fixing

Chaos

Automatic testing

Built-in self-test

Circuit faults

Circuit testing

Cities and towns

Electrical fault detection

Fault detection

Logic design

Test pattern generators

Details

Title: Subtitle: Circuit Independent Weighted Pseudo-Random BIST Pattern Generator
Creators: Chaowen Yu - University of Iowa
Sudhakar M Reddy - University of Iowa
Irith Pomeranz - Purdue University West Lafayette
Resource Type: Conference proceeding
Publication Details: 14th Asian Test Symposium (ATS'05), Vol.2005, pp.132-137
DOI: 10.1109/ATS.2005.37
ISSN: 1081-7735
eISSN: 2377-5386
Publisher: IEEE
Language: English
Date published: 2005
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197192802771

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