Conference proceeding
Compact test generation for bridging faults under I sub(DDQ) testing
The 13th IEEE VLSI Test Symposium; Princeton, NJ; USA; 30 Apr.-03 May 1995, pp.310-316
IEEE VLSI Test Symposium, 13 (Princeton, New Jersey, USA, 04/30/1995–05/03/1995)
04/30/1995
DOI: 10.1109/VTEST.1995.512654
Abstract
We propose a procedure to generate compact test sets for bridging faults under I sub(DDQ) testing. Several techniques are employed to achieve compact test sets. Heuristics developed for stuck-at faults are shown to be effective in this context. The techniques especially designed for bridging faults are based on the observation that the yet-undetected faults can be represented using sets of lines and that a minimum test set size is obtained if the line sets representing yet-undetected faults are halved with every additional test vector. Logic blocks called bit-adders allow the partitioning of the line sets using a test generator for stuck-at faults, without having to determine in advance how the lines in a given set will be divided. Thus partitioning can be performed in a cost effective way for any line set size. Experimental results show that the test sets generated by the proposed procedure are smaller than those obtained by previously proposed procedures.
Details
- Title: Subtitle
- Compact test generation for bridging faults under I sub(DDQ) testing
- Creators
- Remata S ReddyIrith PomeranzSudhakar M ReddySeiji Kajihara
- Resource Type
- Conference proceeding
- Publication Details
- The 13th IEEE VLSI Test Symposium; Princeton, NJ; USA; 30 Apr.-03 May 1995, pp.310-316
- Conference
- IEEE VLSI Test Symposium, 13 (Princeton, New Jersey, USA, 04/30/1995–05/03/1995)
- DOI
- 10.1109/VTEST.1995.512654
- ISSN
- 1093-0167
- Publisher
- IEEE
- Language
- English
- Date published
- 04/30/1995
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984198015802771
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