Conference proceeding
Constraint Driven Pin Mapping for Concurrent SOC Testing
Proceedings of the 2002 Asia and South Pacific Design Automation Conference, pp.511-516
ASP-DAC '02
01/07/2002
DOI: 10.1109/ASPDAC.2002.994971
Abstract
A solution for mapping core I/O pins to System-On-a-Chip (SOC) I/O pins in order to achieve cost-efficient concurrent test for core-based designs is presented in this paper. The problem of pin mapping is first formulated as two well-known NP-complete problems. A heuristic algorithm is then proposed to determine a solution. The objectives driving this solution are geared towards reducing the total number of SOC pins needed and satisfying the test constraints specified by core integrators. Experimental results demonstrate the efficiency of the proposed method.
Details
- Title: Subtitle
- Constraint Driven Pin Mapping for Concurrent SOC Testing
- Creators
- Yu HuangSudhakar ReddyNilanjan MukherjeeChien-Chung TsaiOmer SammanYahya ZaidanYanping ZhangWu-Tung Cheng
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the 2002 Asia and South Pacific Design Automation Conference, pp.511-516
- Series
- ASP-DAC '02
- DOI
- 10.1109/ASPDAC.2002.994971
- Publisher
- IEEE Computer Society
- Language
- English
- Date published
- 01/07/2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197286602771
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