Conference proceeding
Critical performance path analysis, and efficient code generation issues, for the Seamless architecture
[1993] Proceedings Seventh International Parallel Processing Symposium, pp.590-596
1993
DOI: 10.1109/IPPS.1993.262813
Abstract
An analytical study of potential pathological performance areas of the Seamless architecture is presented. Seamless is a latency-tolerant, distributed memory, multiprocessor architecture. A key component of the philosophy of Seamless, however, is the use of standard, commodity components for a large part of the system. A discussion of the unavoidable implementation compromises imposed by this decision is presented, followed by a summary of some optimistic performance studies. Then an analytical study that parameterizes the predicts the worst-case impact of using standard components is provided. Finally, it is shown that these bottlenecks are manageable via careful generation of target machine code so that the optimistic performance studies become realistic expectations for a range of program behaviors and granularities.< >
Details
- Title: Subtitle
- Critical performance path analysis, and efficient code generation issues, for the Seamless architecture
- Creators
- D.L Bright - University of IowaS.A FinebergB.H PeaseM.L RoderickS SundaramT.L Casavant
- Resource Type
- Conference proceeding
- Publication Details
- [1993] Proceedings Seventh International Parallel Processing Symposium, pp.590-596
- DOI
- 10.1109/IPPS.1993.262813
- Publisher
- IEEE Comput. Soc. Press
- Language
- English
- Date published
- 1993
- Academic Unit
- Roy J. Carver Department of Biomedical Engineering; Electrical and Computer Engineering
- Record Identifier
- 9984197202002771
Metrics
12 Record Views