Conference proceeding
Design and synthesis for testability of synchronous sequential circuits based on strong-connectivity
FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing, pp.492-501
Fault Tolerant Computing Symposium (FTCS), 23 (Toulouse, France, 06/22/1993 - 06/24/1993)
1993
DOI: 10.1109/FTCS.1993.627352
Abstract
The importance of strong-connectivity of the state diagram of a circuit in ensuring testability, specifically, in ensuring that no partially detectable faults exist, is shown. Partially detectable faults are irredundant faults that can be detected only if the circuit-under-test starts from specific initial states. They complicate the test generation and test application processes, and are therefore undesirable. Two methods are proposed to ensure that no partially detectable faults exist, through design for testability and through resynthesis of the circuit. Experimental results are presented for both methods. The incorporation of a redundancy removal procedure into the process of eliminating partially detectable faults, to make a circuit fully testable, is also discussed.
Details
- Title: Subtitle
- Design and synthesis for testability of synchronous sequential circuits based on strong-connectivity
- Creators
- I Pomeranz - University of IowaS.M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing, pp.492-501
- Conference
- Fault Tolerant Computing Symposium (FTCS), 23 (Toulouse, France, 06/22/1993 - 06/24/1993)
- Publisher
- IEEE
- DOI
- 10.1109/FTCS.1993.627352
- ISSN
- 0731-3071
- eISSN
- 2375-124X
- Language
- English
- Date published
- 1993
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197998902771
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