Distance restricted scan chain reordering to enhance delay fault coverage

Wei Li; Seongmoon Wang; Srimat T Chakradhar; Sudhakar M Reddy

doi:10.1109/ICVD.2005.83

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Conference proceeding

Distance restricted scan chain reordering to enhance delay fault coverage

Wei Li, Seongmoon Wang, Srimat T Chakradhar and Sudhakar M Reddy

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, pp.471-478

2005

DOI: 10.1109/ICVD.2005.83

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Abstract

This paper presents a new technique to improve the delay fault coverage by re-ordering flip-flops in a scan chain. Unlike prior techniques where scan flip-flops can be reordered arbitrarily to form a new scan chain order, we restrict the distance by which a scan flip-flop can be moved to create the new scan chain order. The distance restriction makes it practical to make post-synthesis, local layout modifications to accommodate the new scan chain order. It also minimizes the routing overhead required for the new scan chain order. Given a post-synthesis scan chain order, we re-order flip-flops to minimize the number of undetectable faults due to test pattern dependency. Although the distance restriction limits the number of possible new scan chain orders, the fault coverage achieved by using our new local scan chain re-ordering method is comparable or even higher than prior methods. Moreover the scan order obtained with our method also improves the coverage of stuck-open faults. Experimental results show that the proposed method can improve delay fault coverage by up to 21.8% for ISCAS 89 circuits.

Circuit faults

Circuit testing

Cities and towns

Fault detection

Flip-flops

Hardware

National electric code

Propagation delay

Routing

Details

Title: Subtitle: Distance restricted scan chain reordering to enhance delay fault coverage
Creators: Wei Li - University of Iowa
Seongmoon Wang - NEC Research Labs#TAB#
Srimat T Chakradhar - NEC Research Labs#TAB#
Sudhakar M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, pp.471-478
Publisher: IEEE
DOI: 10.1109/ICVD.2005.83
ISSN: 1063-9667
eISSN: 2380-6923
Language: English
Date published: 2005
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197325502771

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