Conference proceeding
Dynamic Compaction in SAT-Based ATPG
2009 Asian Test Symposium, pp.187-190
11/2009
DOI: 10.1109/ATS.2009.31
Abstract
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compaction procedure for SAT-based ATPG which utilizes internal data structures of the SAT solver to extract essential fault detection conditions and to generate patterns which cover multiple faults. We complement this technique by a state-of-the-art forward-looking reverse-order simulation procedure. Experimental results obtained for an industrial benchmark circuit suite show that the new method outperforms earlier static approaches by approximately 23%.
Details
- Title: Subtitle
- Dynamic Compaction in SAT-Based ATPG
- Creators
- Alexander Czutro - University of FreiburgIlia Polian - University of FreiburgPiet Engelke - University of FreiburgSudhakar M Reddy - University of IowaBernd Becker - University of Freiburg
- Resource Type
- Conference proceeding
- Publication Details
- 2009 Asian Test Symposium, pp.187-190
- DOI
- 10.1109/ATS.2009.31
- ISSN
- 1081-7735
- eISSN
- 2377-5386
- Publisher
- IEEE
- Language
- English
- Date published
- 11/2009
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197417302771
Metrics
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