Effect of RTL coding style on testability

Yu Huang; Chien-Chung Tsai; N Mukherhee; Wu-Tung Cheng; S.M Reddy

doi:10.1109/CICC.2001.929767

Back

Conference proceeding

Effect of RTL coding style on testability

Yu Huang, Chien-Chung Tsai, N Mukherhee, Wu-Tung Cheng and S.M Reddy

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169), pp.255-258

2001

DOI: 10.1109/CICC.2001.929767

View Online

Abstract

This paper illustrates the effect of functional Register Transfer-Level (RTL) coding styles on the testability of synthesized gate-level circuits. Thus, the advantage of having an RTL code analyzer to reduce the number of untestable faults, thereby improving the overall testability of a design is presented. In addition, it has been also observed that writing efficient RTL code to improve testability reduces the total silicon area of the gate-level circuit as well. Experimental results presented in this paper demonstrate the benefits of having a proposed RTL code analyzer.

Automatic test pattern generation

Circuit faults

Circuit synthesis

Circuit testing

Degradation

Logic design

Logic testing

Redundancy

Signal generators

Silicon

Details

Title: Subtitle: Effect of RTL coding style on testability
Creators: Yu Huang - University of Iowa
Chien-Chung Tsai
N Mukherhee
Wu-Tung Cheng
S.M Reddy
Resource Type: Conference proceeding
Publication Details: Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169), pp.255-258
Publisher: IEEE
DOI: 10.1109/CICC.2001.929767
ISSN: 0886-5930
eISSN: 2152-3630
Language: English
Date published: 2001
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197335402771

Metrics

4 Record Views