Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values

Conference proceeding

Seiji Kajihara, Kewal K Saluja and Sudhakar M Reddy

Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004, pp.108-113

2004

DOI: 10.1109/ETSYM.2004.1347620

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Circuit faults

Circuit simulation

Circuit testing

Computational modeling

Electrical fault detection

Electrons

Fault detection

Logic circuits

Logic testing

Sufficient conditions

Title: Subtitle: Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values
Creators: Seiji Kajihara - Kyushu Institute of Technology
Kewal K Saluja - University of Wisconsin–Madison
Sudhakar M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004, pp.108-113
DOI: 10.1109/ETSYM.2004.1347620
Publisher: IEEE
Language: English
Date published: 2004
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197171102771

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