Conference proceeding
Enhanced untestable path analysis using edge graphs
Proceedings of the Ninth Asian Test Symposium, pp.139-144
Asian Test Symposium, 9 (Taipei, Taiwan, 12/06/2000)
2000
DOI: 10.1109/ATS.2000.893616
Abstract
Logic circuits may have large numbers of untestable paths. Therefore, it is important for path delay fault testing to identify untestable paths prior to test generation. An earlier method, called partial path sensitization, was able to identify large numbers of untestable path delay faults by analyzing pairs of subpaths. We propose to apply this method to the edge graph of the circuit. In the edge graph, an edge corresponds to two consecutive subpaths. Thus, identification of untestable paths is done based on longer subpaths when the edge graph is used than when the original netlist is used. Experimental results presented in this paper show that the proposed method identifies more untestable paths than when the partial path sensitization method is applied to the original netlist.
Details
- Title: Subtitle
- Enhanced untestable path analysis using edge graphs
- Creators
- Seiji Kajihara - Kyushu Institute of TechnologyTakashi ShimonoIrith PomeranzSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the Ninth Asian Test Symposium, pp.139-144
- Conference
- Asian Test Symposium, 9 (Taipei, Taiwan, 12/06/2000)
- DOI
- 10.1109/ATS.2000.893616
- ISSN
- 1081-7735
- eISSN
- 2377-5386
- Publisher
- IEEE
- Language
- English
- Date published
- 2000
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984198004902771
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