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Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG
Conference proceeding

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG

Jan Burchard, Dominik Erb, Adit D Singh, Sudhakar M Reddy and Bernd Becker
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp.422-427
03/2017
DOI: 10.23919/DATE.2017.7927027

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Abstract

Opens are known to be one of the predominant defects in nanoscale technologies. Especially with an increasing number of complex cells in today's VLSI designs intra-gate opens are becoming a major problem. The generation of tests for these faults is hard, as the timing of the circuit needs to be considered accurately to prevent the invalidation of the generated tests through hazards. Current test generation methods, including new cell aware tests that explicitly target open defects, ignore the possibility of hazard caused test invalidation. Such tests can fail to detect a significant fraction of the targeted opens. In this work we present a waveform-accurate hazard-aware test generation approach to target intra-gate opens. Our methodology is based on a SAT-based encoding and allows the generation of tests guaranteed to be robust against hazards. Experimental results for large benchmarks mapped to the state-of-the-art NanGate 45nm cell library including complex cells show the test generation efficiency of the proposed method. Large circuits were efficiently handled - even without the use of fault simulation. Our experiments show that on average, about 10.92 % of conventional hazard-unaware tests will fail to detect the targeted opens because of test invalidation - these are reliably detected by our new test generation methodology. Importantly, our approach can also be applied to improve the effectiveness of commercial cell aware tests.
 Circuit faults Delays Hazards Libraries Logic gates Transistors

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