Fault Diagnosis under Transparent-Scan

Irith Pomeranz; Sudhakar M Reddy

doi:10.1109/ATS.2009.12

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Conference proceeding

Fault Diagnosis under Transparent-Scan

Irith Pomeranz and Sudhakar M Reddy

2009 Asian Test Symposium, pp.29-34

11/2009

DOI: 10.1109/ATS.2009.12

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Abstract

Transparent-scan provides opportunities for test compaction that do not exist with the conventional test application scheme for scan circuits. However, test compaction can reduce the ability of a transparent-scan sequence to diagnose faults. We describe a static test compaction procedure that reduces the length of a transparent-scan sequence while maintaining its stuck-at fault coverage and the number of stuck-at fault pairs it distinguishes. We use the static test compaction process as part of a process that constructs the transparent-scan sequence gradually, using test compaction to prevent the length of the sequence from becoming unnecessarily long.

Circuit faults

Circuit testing

Cities and towns

Clocks

Compaction

Electrical fault detection

Fault detection

Fault diagnosis

scan circuits

Sequential analysis

Sequential circuits

static test compaction

stuck-at faults

transparent-scan

Details

Title: Subtitle: Fault Diagnosis under Transparent-Scan
Creators: Irith Pomeranz - Purdue University West Lafayette
Sudhakar M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 2009 Asian Test Symposium, pp.29-34
DOI: 10.1109/ATS.2009.12
ISSN: 1081-7735
eISSN: 2377-5386
Publisher: IEEE
Language: English
Date published: 11/2009
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197524702771

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