Conference proceeding
Fault diagnosis and fault model aliasing
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), pp.206-211
2005
DOI: 10.1109/ISVLSI.2005.34
Abstract
During fault diagnosis, the existence of equivalent faults, or faults that are not distinguished by the test set applied to the circuit, can create ambiguity as to the location of a defect. This happens if the circuit-under-test produces a response that matches the circuit response in the presence of two faults in different locations of the circuit. Equivalence between faults of different models, or a test set that does not distinguish two such faults, can increase the ambiguity as to the defect location as well as its type. We refer to this phenomenon as fault model aliasing. We study the extent to which fault model aliasing can be expected to occur under various test sets. We also describe a test generation procedure that can reduce it.
Details
- Title: Subtitle
- Fault diagnosis and fault model aliasing
- Creators
- Irith Pomeranz - Purdue University West LafayetteSrikanth Venkataraman - Intel (United States)Sudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), pp.206-211
- DOI
- 10.1109/ISVLSI.2005.34
- ISSN
- 2159-3469
- eISSN
- 2159-3477
- Publisher
- IEEE
- Language
- English
- Date published
- 2005
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197294002771
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