Conference proceeding
Forming multi-cycle tests for delay faults by concatenating broadside tests
2010 28th VLSI Test Symposium (VTS), pp.51-56
04/2010
DOI: 10.1109/VTS.2010.5469616
Abstract
A multi-cycle (or multi-pattern) scan-based test consists of several primary input patterns, which are applied consecutively in functional mode, between scan operations. Multi-cycle tests can reduce the total number of cycles needed to achieve a target fault coverage. Additionally, such tests exercise the circuit in its functional mode of operation during several clock cycles where the primary input patterns are applied. This is important for detecting defects that are not detected with two-pattern scan-based tests. However, a complete test generation process for multi-pattern tests requires sequential test generation. To generate multi-pattern tests with arbitrary numbers of patterns without performing full sequential test generation, and targeting delay faults, we use a broadside test set as a basis for test generation. We introduce the operation of concatenating broadside tests, and describe a procedure that uses it to form multi-cycle tests. We present experimental results demonstrating that the test sets require significantly fewer test cycles than broadside test sets, for the same transition fault coverage.
Details
- Title: Subtitle
- Forming multi-cycle tests for delay faults by concatenating broadside tests
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- 2010 28th VLSI Test Symposium (VTS), pp.51-56
- DOI
- 10.1109/VTS.2010.5469616
- ISSN
- 1093-0167
- eISSN
- 2375-1053
- Publisher
- IEEE
- Language
- English
- Date published
- 04/2010
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197179202771
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