Full scan fault coverage with partial scan

Xijiang Lin; Irith Pomeranz; Sudhakar M Reddy

doi:10.1109/DATE.1999.761167

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Conference proceeding

Full scan fault coverage with partial scan

Xijiang Lin, Irith Pomeranz and Sudhakar M Reddy

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), pp.468-472

1999

DOI: 10.1109/DATE.1999.761167

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Abstract

In this paper, a test generation based partial scan selection procedure is proposed. The procedure is able to achieve the same level of fault coverage as in a full scan design by scanning only a subset of the flip-flops. New measures are used to guide the flip-flop selection during the procedure. The proposed procedure is applied to the ISCAS-89 and the ADDENDUM-93 benchmark circuits. For all the circuits, it is possible to achieve the same fault coverage as that for full scan while scanning a portion of the flip-flops.

Automatic test pattern generation

Benchmark testing

Circuit faults

Circuit testing

Computational efficiency

Electrical fault detection

Fault detection

Fault diagnosis

Feedback loop

Sequential analysis

Details

Title: Subtitle: Full scan fault coverage with partial scan
Creators: Xijiang Lin - Mentor Graphics
Irith Pomeranz
Sudhakar M Reddy
Resource Type: Conference proceeding
Publication Details: Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), pp.468-472
DOI: 10.1109/DATE.1999.761167
ISSN: 1530-1591
eISSN: 1558-1101
Publisher: IEEE
Language: English
Date published: 1999
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197337902771

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