Full-speed field-programmable memory BIST architecture

Xiaogang Du; Nilanjan Mukherjee; Wu-Tung Cheng; Sudhakar M Reddy

doi:10.1109/TEST.2005.1584084

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Conference proceeding

Full-speed field-programmable memory BIST architecture

Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng and Sudhakar M Reddy

IEEE International Conference on Test, 2005, Vol.2005, pp.9 pp-1173

2005

DOI: 10.1109/TEST.2005.1584084

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Abstract

A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of not only March algorithms but also some non-linear algorithms that are becoming more and more important in modern memory testing, diagnosis, and failure analysis

Failure Analysis

Algorithm design and analysis

Built-in self-test

Fault detection

Hardware

Manufacturing

Medical tests

Memory architecture

System-on-a-chip

Testing

Details

Title: Subtitle: Full-speed field-programmable memory BIST architecture
Creators: Xiaogang Du - Mentor Graphics
Nilanjan Mukherjee - Mentor Graphics
Wu-Tung Cheng - Mentor Graphics
Sudhakar M Reddy
Resource Type: Conference proceeding
Publication Details: IEEE International Conference on Test, 2005, Vol.2005, pp.9 pp-1173
DOI: 10.1109/TEST.2005.1584084
ISSN: 1089-3539
eISSN: 2378-2250
Publisher: IEEE
Language: English
Date published: 2005
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197418302771

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