Full-speed field programmable memory BIST supporting multi-level looping

Xiaogang Du; Nilanjan Mukherjee; Wu-Tung Cheng; Sudhakar M Reddy

doi:10.1109/MTDT.2005.25

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Conference proceeding

Full-speed field programmable memory BIST supporting multi-level looping

Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng and Sudhakar M Reddy

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05), pp.67-71

2005

DOI: 10.1109/MTDT.2005.25

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Abstract

A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of algorithms containing more than one level of looping.

Failure Analysis

Algorithm design and analysis

Built-in self-test

Fault detection

Manufacturing

Production

Programmable control

Random access memory

System-on-a-chip

Testing

Details

Title: Subtitle: Full-speed field programmable memory BIST supporting multi-level looping
Creators: Xiaogang Du - Mentor Graphics
Nilanjan Mukherjee - Mentor Graphics
Wu-Tung Cheng - Mentor Graphics
Sudhakar M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05), pp.67-71
DOI: 10.1109/MTDT.2005.25
ISSN: 1087-4852
eISSN: 2576-9154
Publisher: IEEE
Language: English
Date published: 2005
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197357902771

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